Memories comprise one of the largest markets for semiconductor integrated circuits. In general, a memory is a storage device that retains information or data that can be output when needed. Memory devices are often characterized under such names as high speed, high density, or non-volatile memories. A high speed memory, as its name implies is a device having extremely fast read/write times that are useful in situations where data transfer rates are critical. A high density memory has a substantial memory size for large storage capability. The most common high density solid state memory is a dynamic random access memory (DRAM). A non-volatile memory is a memory that retains information even when power is removed and is thereby a permanent storage medium. A common non-volatile memory is FLASH memory. In general, an ideal memory has characteristics of all of the above mentioned types of memory.
As mentioned previously, the most widely used non-volatile memory is FLASH memory. FLASH memory uses charge storage in a floating gate to retain information. FLASH memories operate at relatively high voltages, running counter to the trend of reducing power supply voltages for other high density integrated circuits. Moreover, they have slow program and erase times. The ability to write or store charge in the floating oxide is limited to a finite number of times that can be exceeded depending on the application. Memory failure occurs if the maximum number of writes is exceeded. FLASH memory is limited for high density applications because it cannot be continually scaled to smaller dimensions due to gate oxide limitations.
Another type of non-volatile memory is a magnetoresistive random access memory (MRAM). MRAM is a viable memory type for the future because it is a high density memory, scalable, low voltage, low power consumption, and high speed read/write times. A magnetoresistive memory cell comprises a magnetic tunnel junction (MTJ) and includes ferromagnetic layers separated by an insulating dielectric. Electrons tunnel through the dielectric, known as the tunnel barrier, from a first ferromagnetic layer to a second ferromagnetic layer. The direction of the magnetization vectors in the ferromagnetic layers determines the tunneling resistance. A zero logic state is represented when the magnetization directions are parallel which corresponds to a low tunneling resistance for the magnetic tunneling junction. Conversely, a one logic state is represented when the magnetization states are anti-parallel which corresponds to a high tunneling resistance. Typically, a magnetic vector in one magnetic layer is fixed or pinned, while the magnetization direction of the other magnetic layer is free to switch between the same and opposite (anti-parallel) directions. The memory is non-volatile because the ferromagnetic material holds the magnetization vectors when the memory is not powered. It should be noted that the selection of the parallel state or the anti-parallel state as a logic one or zero state is arbitrary.
In a common MRAM architecture, each memory cell of an array of memory cells is located at the intersections of an orthogonal array of conductive lines. A bit line is generally associated with each column of an array of MRAM cells and a digit line is associated with each row of MRAM cells in the array. In general, programming or writing to a selected cell is accomplished by passing predetermined currents through the digit and bit lines intersecting at the selected cell. The currents create a magnetic field that sets the magnetic vector in the free layer to a desired position. Reading the state of a MRAM cell is accomplished by detecting a resistance of the magnetic tunnel junction (MTJ). For example, the MRAM cell is biased at a predetermined voltage, the magnitude of the current through the MRAM cell corresponds to the resistance value of the device. Thus, the two different resistive values of the MRAM cell that directly relates to a stored parallel or anti-parallel magnetization vector can be converted to a corresponding digital logic level.
In general, MRAM cells are formed in a CMOS wafer process. In many MRAM architectures, each memory cell has at least one CMOS transistor coupled in series to the cell. In development or production manufacturing it is beneficial to be able to rapidly characterize and optimize memory cells with the supporting CMOS circuitry. This is especially true when the goal is the characterization of the MRAM cell itself and not other circuitry associated with the memory. The cost to process wafers to a finished level is expensive because of the number of masks and wafer processing steps required in a complex CMOS wafer process flow. Moreover, in the development phase, different materials or different cell structures are routinely produced that if processed using the entire process flow would have substantial manufacturing cycle time. Long term, it is beneficial to have the capability to perform on chip testing of MRAM cells during wafer processing and at wafer probe to generate insitu processing data.
Accordingly, it is desirable to provide a test apparatus for characterizing a MRAM cell. In addition, it is desirable to reduce the cost to develop MRAM cells. It would be of further benefit to provide a test methodology to characterize MRAM cells in a production environment. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.